Responsibility: 

1. Architect, implement and support synthesis/Formal check/Low power check flow; 

2. Be responsible for block level or top level synthesis and netlist deliver; 

3. Be responsible for block level or top level SDC structure and flow, work with RTL Designer/DFT engineer for SDC delivery and quality check; 

4. Be responsible for chip level timing signoff，work with PR Engineer for timing closure.

Requirements: 

1. Bachelor degree or above, major in ME/EE/CS , with 3-5 years of experience in synthesis or STA; 

2. Strong experience in Synthesis/Formal/STA flow; 

3. familiar with 7nm and other advanced nodes mv timing signoff; 

4. Experience with scripting and automation, Good logic and problem-solving skills; 5. Strong communication skills, teamwork experience and a quick learner in a fast-moving environment.

Responsibility: 

1. Be responsible for block level or top level floorplan, power-mesh, timing closure, power analysis, physical verification and other APR work; 

2. Be responsible for static timing analysis and IR-Drop/EM signoff at block or top level; 

3. Be responsible for physical verification signoff like DRC/ERC/LVS, etc. at block or top level;

Requirements: 

1. Bachelor degree or above, major in ME/EE/CS , with 3-5 years of experience in physical design; 

2. Good script skills required(such as tcl, Perl, python, etc.); 

3. Be familiar with EDA tools (Cadence/Synposys, such as ICC2, Innovus, Star-rc,PT, Calibre,Redhawk/Voltus), and be familiar with advanced process like16/7nm and other advanced nodes; 

4. Good communication skills, teamwork spirits, fluent in English reading and writing.

Responsibility: 

1. Work closely with Architecture, Systems & Design teams to deliver a bug free complex SoC; 

2. Architect, implement and support Design Verification Flows, Infrastructure and Tools; 

3. Develop SV/UVM based testbenches for IP and SoC level DV;

4. Own and execute verification for critical blocks in the SoC.

Requirements: 

1. BS w/ 5+ years or MS w/ 3+ years of experience in IP/SoC DV; 

2. Experience in FV(Formal verification) and/or SV/UVM; 

3. Knowledge of SerDes, DDR, PCIE, CPU Subsystem; 

4. Experience with scripting and automation, Good logic and problem-solving skills; 

5. Strong communication skills, teamwork experience and a quick learner in a fast-moving environment.

Responsibility: 

1. SoC Integration of Server Processor with CPU, Bus Interconnects, Peripherals; 

2. Work closely with Architecture/Systems/Verification/Software teams to achieve high quality IP/SoC delivery; 

3. Quality checks of the implemented RTL for LINT, CDC rules & documentation of implementation, exceptions and waivers; 

4. Provide support in simulation, emulation, and silicon environments.

Requirements: 

1. BS w/ 5+ years or MS w/ 3+ years of experience in RTL Design; 

2. Must have experience in RTL level ASIC design, including use of a source control system and RTL linting tools, as well as be able to debug RTL code using simulation tools; 

3. Knowledge of ARM microprocessor architecture; 

4. Experience with scripting and automation, Good logic and problem-solving skills; 

5. Strong communication skills, teamwork experience and a quick learner in a fast-moving environment.